1. Technical Field
The present invention relates specifically to a phase modulation apparatus, polar modulation transmission apparatus, wireless transmission apparatus and wireless communication apparatus that perform phase modulation utilizing the PLL (Phase Locked Loop).
2. Description of the Related Art
Heretofore, phase modulation apparatuses utilizing the PLL have been widely used to modulate carrier signals by baseband modulation signals and form transmission signals (that is, to up-convert baseband modulation signals to radio frequency). Generally, phase modulation apparatuses of this type are expected to realize low costs, low power consumption, excellent noise characteristics, and high modulation accuracy. To modulate signals using the PLL, and, in particular, to improve modulation accuracy using the PLL, the PLL frequency bandwidth (i.e. PLL bandwidth) is preferably wider than the frequency bandwidth of the modulation signal (i.e. modulation bandwidth).
However, widening the PLL bandwidth has the risk of deteriorating noise characteristics. So, the technology called “two-point modulation” is presently proposed whereby the PLL bandwidth is set narrower than the modulation bandwidth, and the modulation within the PLL bandwidth and the modulation outside the PLL bandwidth are performed at two different points (see, for example, U.S. Pat. No. 4,308,508).
FIG. 1 shows the configuration of a phase modulation apparatus utilizing conventional two-point modulation PLL. Phase modulation apparatus 10 has: a voltage controlled oscillator (VCO) 1 that changes the oscillation frequency in accordance with the voltage in the control voltage terminal; frequency divider 2 that divides the frequency of an RF phase modulation signal outputted from VCO 1; phase detector 3 that compares the phase of the output signal of frequency divider 2 with the phase of a reference signal and outputs a signal in accordance with the phase different between the two signals; and loop filter 4 that equalizes the output signal of phase detector 3 and outputs the result. Phase modulation apparatus 10 adds a phase modulation signal generated in modulation signal generator 5 to carrier frequency data and supplies the result as the frequency division ratio in frequency divider 2, thereby performing modulation at the first point.
In addition, phase modulation apparatus 10 lets the phase modulation signal pass through post filter 6 and thereafter adds the phase modulation signal to the output of loop filter 4, and supplies the result to the control voltage terminal of VCO 1, thereby performing modulation at the second point.
The use of the two-point frequency modulation technology such as described above makes it possible to output wideband RF modulation signals that stretch outside the PLL bandwidth, even when the PLL bandwidth is set narrower than the modulation bandwidth. As a result, the deterioration in noise characteristics due to the PLL is minimized.
FIG. 2 shows frequency characteristics in baseband domain for explanation of the operation of two-point modulation PLL. H(s) is a transfer function that indicates the frequency characteristics of the PLL, where s=jω. H(s) has low pass characteristics, such as shown in FIG. 2. The modulation signal added to the frequency division ratio set in frequency divider 2 is low pass filtered by the transfer function H(s) by the PLL. On the other hand, the modulation signal outputted from post filter 6 is added to the control voltage terminal of VCO 1 and thereby high pass filtered by the transfer function 1-H(s), such as shown in FIG. 2. That is, if the modulation signal is Φ (s), the baseband component in the RF modulation signal outputted from VCO 1 bears no relationship to the frequency characteristics of the PLL, as shown by the following formula:H(s)Φ(s)+{1−H(s)}Φ(s)=Φ(s)  (1)
Applying two-point modulation thus to the PLL makes it possible to output wideband RF modulation signals that stretch outside the PLL bandwidth, from VCO 1. Incidentally, fs is the sampling frequency.
However, when the kind of configuration disclosed in the specification of above U.S. Pat. No. 4,308,508 is employed, if VCO 1 is integrated in LSI, element values vary due to the nature of manufacturing. As a result, modulation sensitivity varies in each LSI. The modulation sensitivity varies also by temperature. When the modulation sensitivity of VCO 1 varies, this makes it difficult to obtain desired output signals (i.e. RF modulation signals). Now, FIG. 3 illustrates an ideal VCO output signal, and FIG. 4 illustrates a VCO output signal where the modulation sensitivity varies.
As a solution to the above-noted problem, there is a phase modulation apparatus disclosed in U.S. Pat. No. 5,952,895. This phase modulation apparatus is also one of the two point modulation PLL type and yet differs from the configuration disclosed in patent document 1 in that the modulation at the first point is performed by modulating a reference signal.
FIG. 5 illustrates the configuration of the phase modulation apparatus disclosed in patent document 2. Phase modulation apparatus 20 has: a voltage controlled oscillator (VCO) 21 that changes the oscillation frequency in accordance with the voltage in the control voltage terminal; down converter 25 comprised of mixer 22, synthesizer 23 and low pass filter (LPF) 24; frequency divider 26 that divides the frequency of a down-converted RF phase modulation signal; phase detector (PD) 27 that compares the phase of the output signal of frequency divider 26 with the phase of a reference signal and outputs a signal in accordance with the phase difference between the two signals; and loop filter (LPF: Low Pass Filter) 28 that equalizes the output signal of phase detector 27.
In addition, phase modulation apparatus 20 has direct digital synthesizer (DDS) 30. Based on a baseband input phase modulation signal, direct digital synthesizer 30 forms a phase modulation signal having the reference frequency at the center frequency, and sends this phase modulation signal to phase comparator 27 as a reference signal, thereby performing modulation at the first point.
In addition, phase modulation apparatus 20 adds the input phase modulation signal to the output of loop filter 28 by adder 31 and supplies the voltage of the signal after the addition to the control voltage terminal of VCO 101, thereby performing modulation at the second point.
Furthermore, phase modulation apparatus 20 has: phase detector 32 that performs phase detection with respect to the phase modulation signal outputted from low pass filter 24; comparator 33 that compares the detected signal with the baseband phase modulation signal and outputs the difference; and variable gain amplifier 34 that controls the gain of the baseband phase modulation signal based on the output of comparator 33 and supplies the gain-controlled baseband phase modulation signal to voltage controlled oscillator 21 in later stage of loop filter 28. In actuality, the baseband phase modulation signal subjected to gain control in variable gain amplifier 34 is added to the output of loop filter 28 in adder 31 and the result is supplied to voltage controlled oscillator 21.
Thus, in the above configuration, when a compassion result is obtained in comparator 33 that the signal level of the phase modulation signal is greater than the signal level of the phase detection signal, variable gain amplifier 34 increases the gain according to the difference value. If, in comparator 33, a comparison result is obtained that the signal level of the phase modulation signal is lower than the signal level of the phase detection signal, variable gain amplifier 34 lowers the gain according to the difference value.
As a result, phase modulation apparatus 20 makes it possible to adjust the modulation level automatically even when the modulation sensitivity of voltage controlled oscillator 21 varies.
However, to achieve good modulation accuracy characteristics in phase modulation apparatus 20 having the configuration of FIG. 5, the resolution of DDS 30 needs to be set high. However, increasing the resolution requires high speed clock, which gives a rise to another problem of increased power consumption.
In addition, the tradeoff with power consumption and the maximum operation frequency of the circuit set further limitations to increasing the clock, and so, in reality, the DDS output frequency cannot be heightened much. As a result, the PLL bandwidth needs to be made narrow, which gives a rise to yet another problem of increased PLL lock up time.